Recently, as a Large Scale Integrated circuit (LSI) increases in its scale, the LSI has become mainstream for layered LSI design to be conducted by using a plurality of layers. With layered LSI design, there is known technology that ascertains net connection information between layers by assigning codes (net codes) that identify net types (such as for clock signals and for test signals, etc.) to logical connection information (logical nets) that define connections between the terminals of respective elements such as transistors, for example.
The assignment of net codes is for example conducted for each layer on the basis of layer pin codes that take into account the effects of other layers on the layer pins of the current layer. Layer pin codes are codes that set layer pins, and include net code trace information.
However, if layer pin codes are assigned manually, there is a problem in that layer-to-layer interface consistency may not be obtained due to incorrect layer pin code specification. Literature related to design support apparatus and design support methods is given in the patent document listed below.
[Patent Document 1] Japanese Laid-open Patent Publication No. 5-290113
[Patent Document 2] Japanese Laid-open Patent Publication No. 2-025980